Что (кто) такое VHDL - определение

The VHSIC Hardware Description Language (VHDL) is a hardware description language (HDL) that can model the behavior and structure of digital systems at multiple levels of abstraction, ranging from the system level down to that of logic gates, for design entry, documentation, and verification purposes. Since 1987, VHDL has been standardized by the Institute of Electrical and Electronics Engineers (IEEE) as IEEE Std 1076; the latest version of which is IEEE Std 1076-2019. To model analog and mixed-signal systems, an IEEE-standardized HDL based on VHDL called VHDL-AMS (officially IEEE 1076.1) has been developed.

VHDL is named after the United States Department of Defense program that created it, the Very High Speed Integrated Circuits Program (VHSIC). In the early 1980s, the VHSIC Program sought a new HDL for use in the design of the integrated circuits it aimed to develop. The product of this effort was VHDL Version 7.2, released in 1985. The effort to standardize it as an IEEE standard began in the following year.

VHDL, developed in 1983 at the request of the U.S. Department of Defense, is used to document and simulate the behavior of ASICs in electronic equipment. The language has undergone multiple revisions and has numerous sub-standards associated with it that extend its functionality. VHDL borrows heavily from the Ada programming language in terms of syntax and concepts.

The initial version of VHDL (IEEE 1076-1987) included a wide range of data types. Subsequent updates and child standards have further extended the language's capabilities. In 2008, VHDL 4.0 (informally known as VHDL 2008) was approved, addressing issues from the trial period of version 3.0 and enhancing generic types.

VHDL is commonly used to write text models that describe logic circuits, which are then processed by synthesis programs and tested using simulation models in a testbench. The language has constructs to handle parallelism inherent in hardware designs and includes features specific to hardware operations. Although VHDL can be used for text processing, it is more commonly utilized in simulation testbenches for stimulus or verification data.

VHDL is used for system design, modeling, and verification before synthesis into hardware. It allows concurrent system descriptions and is considered a dataflow language with simultaneous statement execution. VHDL projects are multipurpose, portable, and have a full type system. Designs consist of an entity (interface) and architecture (implementation). VHDL is used for simulation and synthesis of electronic designs, with a common synthesizable subset. However, not all constructs are suitable for synthesis, and some are simulation-only.